How to Write a SystemVerilog Constraint to Generate the Pattern 1234554321

Welcome to VLSI 360, your go-to resource for VLSI design, verification, and SystemVerilog tutorials! In this blog post, we’ll dive into a common SystemVerilog interview question: "Write a constraint to generate the pattern 1234554321 using an array in SystemVerilog." This question is popular in VLSI verification interviews, and we’ll break it down step-by-step to help you understand the solution. Whether you're a beginner or an experienced engineer, this guide will provide you with a clear and concise solution.

Understanding the Problem: Generate the Pattern 1234554321

The task is to write a SystemVerilog constraint that generates the sequence 1234554321 in an array of size 10. The pattern starts at 1, increases to 5, and then decreases back to 1, following a symmetric structure. Let’s break it down:

• Array size: 10 elements
• Pattern: 1, 2, 3, 4, 5, 5, 4, 3, 2, 1
• Constraint requirement: Use a SystemVerilog rand array and enforce this pattern.

Step-by-Step Solution in SystemVerilog

Below is the SystemVerilog code to achieve this pattern using a constraint. This solution uses a rand array and a foreach loop to define the pattern.

class pattern_generator;
  rand bit [3:0] pattern_array[10];

  // Define a constraint to generate the required pattern
  constraint pattern_constraint {
    foreach (pattern_array[i]) {
      if (i < 5)         pattern_array[i] == i + 1;  
      else                pattern_array[i] == 10 - i; 
    }
  }
endclass

module test;
  initial begin
   
    pattern_generator p_inst = new();

    if (p_inst.randomize())
      $display("Generated Pattern: %p", p_inst.pattern_array); 
    else
      $display("Randomization failed"); 
  end
endmodule

Explanation of the Updated Code

1. Class Definition: The class pattern_generator contains a rand array pattern_array of size 10. Each element is a 4-bit value (bit [3:0]) to hold numbers from 1 to 5.
2. Constraint Logic:
   • The foreach loop iterates over the array indices (i from 0 to 9).
   • For indices 0 to 4 (i < 5), the value is set to i + 1 (i.e., 1, 2, 3, 4, 5).
   • For indices 5 to 9 (i >= 5), the value is set to 10 - i (i.e., 5, 4, 3, 2, 1).
3. Testbench: The initial block creates an instance p_inst of the class, calls randomize(), and displays the generated pattern.

When you run this code, the output will be:

Generated Pattern: '{1, 2, 3, 4, 5, 5, 4, 3, 2, 1}

Why This Solution is Effective

• The foreach loop ensures the pattern is enforced across all array elements in a concise way.
• The use of descriptive names like pattern_generator and pattern_array improves code readability, which is a good practice in VLSI verification.
• The constraint logic is simple and efficient, making it easy to modify for similar patterns.

Common Interview Follow-Up Questions

When preparing for VLSI verification interviews, you might encounter related questions such as:

• How would you modify the constraint to generate a different pattern, like 123454321?
• Can you write the same constraint without using a foreach loop?
• How would you add assertions to verify the generated pattern?

For example, to verify the pattern, you could add a post-randomization check in the class to compare pattern_array with the expected sequence.