Efficient Multiplication in Verilog Using Left Shift Operators

byKarankumar May 01, 2025

Efficient Multiplication in Verilog Using Left Shift Operators


Introduction

Multiplication in digital design can be efficiently performed using left shift operators in Verilog, especially to minimize code and calculations. In this blog, we’ll multiply two numbers, a = 63 and b = 7, using the left shift method. We’ll also include a second example, 63 ×10, to ensure clarity. We select (a) as the number requiring more bits (63 needs 6 bits, while 7 needs 3 bits), following the convention to optimize the process.


Step 1: Select Numbers (a) and (b)

We are given:
  • a = 63
    , which requires 6 bits (since
    63 = (111111
    )2).
  • b = 7
    , which requires 3 bits (since
    7 = (111)2).
We choose
a = 63
and
b = 7
because (a) requires more bits, reducing the number of iterations. We’ll also compute
63×10
as a second example, where (10) requires 4 bits (
10 = (1010)2).

Step 2: Convert (b) to Binary and Identify True Values

Example 1:
b = 7

Convert
b = 7
to binary:
  • 7 = (111)2
Identify positions with a true value (1):
  • Position 2 (
    2^2
    ): 1 (true)
  • Position 1 (
    2^1
    ): 1 (true)
  • Position 0 (
    2^0
    ): 1 (true)
True values are at
2^2
,
2^1
, and
2^0
.
Example 2:
b = 10

Convert
b = 10
to binary:
  • 10 = 1010_2
    .
Identify positions with a true value (1):
  • Position 3 (
    2^3
    ): 1 (true)
  • Position 2 (
    2^2
    ): 0 (false)
  • Position 1 (
    2^1
    ): 1 (true)
  • Position 0 (
    2^0
    ): 0 (false)
True values are at
2^3
and
2^1
.

Step 3: Multiply Using Left Shifts

Example 1:
63×7=?

For each position where
b = 7
has a 1, left shift
a = 63
by that position’s power and add the results:
  • Position 2 (
    2^2
    ):
    63 << 2
  • Position 1 (
    2^1
    ):
    63 << 1
  • Position 0 (
    2^0
    ):
    63 << 0
The multiplication result is:
Result = (63 << 2) + (63 << 1) + (63 << 0)

Calculate:
  • 63 << 2 = 252
  • 63 << 1 = 126
  • 63 << 0 = 63
Add them: 252 + 126 + 63 = 441
So,
63×7 = 441
.
Example 2:
63×10

For each position where
b = 10
has a 1, left shift
a = 63
by that position’s power and add the results:
  • Position 3 (
    2^3
    ):
    63 << 3
  • Position 1 (
    2^1
    ):
    63 << 1
The multiplication result is:
Result = (63 << 3) + (63 << 1)

Calculate:
  • 63 << 3 = 504
  • 63 << 1 = 126
Add them: 504 + 126 = 630
So,
63×10 = 630
.

Verilog Code


module top;
  integer result;
  
  initial begin
    // multiplication of 63 and 7
    result = (63<<2) + (63<<1) + (63<<0);
    $display  ("==> 63×7:%0d",result);
    
    // multiplication of 63 and 10
    result = (63<<3) + (63<<1);
    $display  ("==> 63×10:%0d",result);
  end
  
endmodule


Output

Running the above code produces the following results 
    ==> 63x7:441
    ==> 63x10:630

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