5 Verilog Interview Questions for VLSI: Blocking, Wire, Always & More

Welcome to the first blog in our VLSI 360 Verilog Interview Series! If you're preparing for a VLSI interview, mastering Verilog is a must. In this post, we cover five common Verilog interview questions to help you grasp key concepts. Each answer is clear, concise, and beginner-friendly, perfect for students and engineers. Let’s dive in and boost your VLSI prep!

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Question 1: What is difference between "Blocking" and "Non-Blocking" assignments?

• Blocking Assignments:
  • Use = (e.g., a = 5;).
  • Execute sequentially, one after another.
  • Evaluate the right-hand side (RHS) and update the left-hand side (LHS) immediately.
  • Block other assignments until the current one finishes.
  • Named “blocking” due to this behavior.
  • Best for combinational logic or testbenches.
• Non-Blocking Assignments:
  • Use <= (e.g., a <= 5;).
  • Start by evaluating the RHS at the beginning of a time slot.
  • Schedule LHS update at the end of the time slot.
  • Allow other Verilog statements to execute between RHS evaluation and LHS update.
  • Called “non-blocking” because it doesn’t block other assignments.
  • Best for sequential logic like flip-flops.
• Key Point: Blocking (=) is sequential and immediate; non-blocking (<=) is parallel and scheduled.

Example:

always @(posedge clk) begin
  a = 5;   // Blocking: a updates now
  b <= 10; // Non-blocking: b updates later
end

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Question 2: What is difference between "wire" and "reg"?

• Wire (Net Type):
  • Used for physical connections between structural elements (e.g., wires, tri).
  • Assigned by continuous assignment, gate output, or module port.
  • Cannot store values; values are read or assigned.
  • Default value is z (high impedance).
• Reg (Register Type):
  • Represents abstract data storage (e.g., reg, integer, time, real, real-time).
  • Not physical registers, just a modeling construct.
  • Assigned only in always or initial statements.
  • Can store values.
  • Default value is x (unknown).
• Key Point: Use wire for structural connections; use reg for procedural storage.

Example:

wire w;
reg r;
assign w = a & b; // Wire driven continuously
always @(posedge clk)
  r <= a & b;     // Reg stores value

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Question 3: What is an "automatic" keyword in the task?

• Definition: The automatic keyword specifies a task’s variable scope.
• Behavior: Memory is allocated for variables when the task starts and deallocated when it ends.
• Scope: Variables are local to each task call unless declared as static.
• Use: Prevents conflicts in concurrent task calls.
• Key Point: automatic makes tasks safe for multiple simultaneous calls.

Example:

task automatic add(input integer x, output integer y);
  integer temp;
  temp = x + 1; // Local variable, no conflicts
  y = temp;
endtask

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Question 4: What is the difference between task and function in Verilog?

• Task:
  • Can include delays (e.g., #10).
  • Supports input, output, and inout arguments.
  • Used in procedural blocks like always or initial.
• Function:
  • Cannot include delays; executes instantly.
  • Returns a single value; supports only input arguments.
  • Used in expressions or procedural blocks.
• Key Point: Tasks handle complex operations with delays; functions provide quick results.

Example:

task my_task(input a, output b);
  #5 b = a + 1; // Task with delay
endtask

function integer my_func(input integer a);
  my_func = a + 1; // Function returns value
endfunction

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Question 5: What is the significance of the "always" block in Verilog?

• Definition: The always block runs repeatedly based on its sensitivity list.
• Purpose: Models combinational or sequential logic.
• Types:
  • @(posedge clk) for clocked (sequential) logic.
  • @(*) for combinational logic.
• Key Point: always defines how hardware reacts to signal changes.

Example:

always @(posedge clk)
  q <= d; // Sequential: updates q on clock edge

always @(*)
  y = a & b; // Combinational: updates y instantly