SystemVerilog Constraints for 3 Unique Numbers No Unique

Welcome back to VLSI 360, your go-to resource for VLSI design, verification, and SystemVerilog tutorials! Today, we’re tackling a straightforward problem: generating three unique numbers in the range [1:3] using SystemVerilog constraints without the unique keyword. This is a great exercise for mastering randomization and constraints, a common topic in VLSI verification interviews and academic projects. We’ll walk through the provided working code, explain its logic, and share tips to help you shine. Let’s dive in!

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Question: Write SystemVerilog Constraints to Generate Three Unique Numbers Without Using "unique"

We need to generate three variables (a, b, c) in SystemVerilog with the following properties:

• Each variable must be in the range [1:3] (i.e., 1, 2, or 3).
• All three variables must have distinct values (e.g., if a = 1, then b and c cannot be 1).
• The unique constraint cannot be used; instead, we must enforce uniqueness with explicit constraints.

Our goal is to write SystemVerilog constraints to generate these unique numbers and display multiple random combinations. The provided code is verified to work, so let’s analyze it.

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SystemVerilog Constraints for Three Unique Numbers

Below is the working SystemVerilog code to generate three unique numbers using a class-based approach with constraints.

class sample;
  rand int a, b, c;  // Variables for three unique numbers
  
  function void print();
    $display("a:%0d  ||  b:%0d  ||  c:%0d", a, b, c);    
  endfunction
  
  constraint cons {
    a inside {[1:3]};  // a in range [1:3]
    b inside {[1:3]};  // b in range [1:3]
    c inside {[1:3]};  // c in range [1:3]
    a != b;            // a and b are different
    b != c;            // b and c are different
    a != c;            // a and c are different
  }
endclass
  
module tb;
  sample s;
  
  initial begin
    s = new();
    repeat (5) begin
      assert(s.randomize());
      s.print();
    end
  end
endmodule

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How It Works

Let’s break down the code to understand how it generates three unique numbers in the range [1:3].

Class Definition (sample):

• The sample class encapsulates the logic for generating the three numbers.
• Variables: rand int a, b, c are three random integers to hold the unique values. The rand keyword enables randomization with constraints.

Value Constraints (cons):

• a inside {[1:3]}: Restricts a to the values 1, 2, or 3.
• b inside {[1:3]}: Restricts b to the values 1, 2, or 3.
• c inside {[1:3]}: Restricts c to the values 1, 2, or 3.
• a != b: Ensures a and b have different values.
• b != c: Ensures b and c have different values.
• a != c: Ensures a and c have different values.
• These inequality constraints collectively guarantee that a, b, and c are distinct without using the unique keyword.

Print Function:

• Displays the values of a, b, and c in a formatted string using $display.
• The format "a:%0d || b:%0d || c:%0d" makes the output clear and readable.

Top Module (tb):

• Instantiates the sample class.
• Calls randomize() five times in a repeat loop to generate different valid combinations of a, b, and c.
• Prints each combination using the print function.

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Output

Running the code produces five different random combinations of three unique numbers in the range [1:3]. A sample output might look like:

a:1  ||  b:2  ||  c:3
a:2  ||  b:3  ||  c:1
a:3  ||  b:1  ||  c:2
a:1  ||  b:3  ||  c:2
a:2  ||  b:1  ||  c:3

Each combination satisfies:

• All values are in [1:3].
• All three values (a, b, c) are distinct.
• The output shows valid permutations of {1, 2, 3}, as there are exactly

  3! = 6

  possible combinations.

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Tips for Interviews

This problem is a great fit for VLSI verification interviews, as it tests:

• Constraint writing for ensuring uniqueness without the unique keyword.
• Randomization techniques in SystemVerilog.
• Understanding of basic permutation logic.

Potential follow-up questions include:

• Can you extend the range to [1:4] and maintain uniqueness?
• How would you verify that all possible combinations are generated over multiple runs?
• Can you modify the code to use an array instead of individual variables?
• How would you handle a larger set of numbers with similar constraints?

For verification, you can add a function to check the constraints:

systemverilog

function void check_values();
  assert(a inside {[1:3]}) else $error("a out of range: %0d", a);
  assert(b inside {[1:3]}) else $error("b out of range: %0d", b);
  assert(c inside {[1:3]}) else $error("c out of range: %0d", c);
  assert(a != b && b != c && a != c) else $error("Uniqueness failed: a=%0d, b=%0d, c=%0d", a, b, c);
endfunction

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Conclusion

Generating three unique numbers in the range [1:3] without using the unique keyword in SystemVerilog constraints is a simple yet powerful way to practice randomization and constraint-based programming. The provided code is verified to work and is ideal for VLSI verification interviews or academic projects. Experiment with it by modifying the range or adding verification checks to enhance your skills.

Keep following VLSI 360 for more SystemVerilog tutorials and VLSI insights! Drop a comment if you have questions or want another topic covered. Happy coding!