5 Verilog Interview Questions for Verilog Part-2: Sequential and Combinational, Sensitivity List, Procedural Blocks, FSM, Case Statement

Welcome to the second blog in our VLSI 360 Verilog Interview Series! If you're preparing for a VLSI interview, mastering Verilog is a must. In this post, we cover five common Verilog interview questions to help you grasp key concepts. Each answer is clear, concise, and beginner-friendly, perfect for students and engineers. Let’s dive in and boost your VLSI prep!

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Question 1: What is the difference between combinational and sequential logic in Verilog?

• Combinational Logic:
  • Output depends only on current inputs.
  • No memory or clock involved.
  • Modeled using always @(*) or continuous assignments.
• Sequential Logic:
  • Output depends on current inputs and past states.
  • Uses memory (e.g., flip-flops) and a clock.
  • Modeled using always @(posedge clk).
• Key Point: Combinational logic is memoryless; sequential logic stores history.

Example:

// Combinational
always @(*)
  y = a & b;

// Sequential
always @(posedge clk)
  q <= d;

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Question 2: What is a sensitivity list in Verilog?

• Definition: A sensitivity list determines when an always block runs.
• Types:
  • @(*): Runs for any change in inputs (combinational).
  • @(posedge clk): Runs on clock edge (sequential).
  • Specific signals: Runs when listed signals change (e.g., @(a or b)).
• Use: Ensures the block reacts to the right signals.
• Key Point: Choose the sensitivity list based on logic type.

Example:

always @(a or b)  // Runs when a or b changes
  y = a | b;

always @(posedge clk)  // Runs on clock rising edge
  q <= d;

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Question 3: What is the difference between initial and always blocks in Verilog?

• Initial Block:
  • Runs only once at simulation start.
  • Used for initialization (e.g., setting variables).
  • Common in testbenches.
• Always Block:
  • Runs repeatedly based on its sensitivity list.
  • Used for modeling logic (combinational or sequential).
  • Common in design code.
• Key Point: initial is for setup; always is for ongoing behavior.

Example:

initial begin
  a = 0;  // Set a at start
end

always @(posedge clk)
  a <= a + 1;  // Update a every clock

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Question 4: What is a finite state machine (FSM) in Verilog?

• Definition: An FSM is a model with defined states, transitions, and outputs.
• Components:
  • States: Represent system modes (e.g., idle, active).
  • Transitions: Rules to move between states.
  • Outputs: Depend on states and/or inputs.
• Types:
  • Moore: Output depends only on state.
  • Mealy: Output depends on state and inputs.
• Key Point: FSMs control sequential behavior in designs.

Example:

reg [1:0] state;
always @(posedge clk) begin
  case (state)
    0: state <= 1;  // Move to next state
    1: state <= 2;
    2: state <= 0;
  endcase
end

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Question 5: What is the role of the case statement in Verilog?

• Definition: The case statement selects one block of code based on a variable’s value.
• Use: Simplifies multi-choice logic (like a switch).
• Features:
  • Matches the expression to listed cases.
  • Executes the matching case’s code.
  • Default case handles unmatched values.
• Key Point: Use case for clear, readable state or control logic.

Example:

always @(*) begin
  case (sel)
    2'b00: out = in0;
    2'b01: out = in1;
    2'b10: out = in2;
    default: out = 0;
  endcase
end

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Read More: Part-I [5 Verilog Interview Questions for VLSI: Blocking, Wire, Always & More]