Verilog Syntax

Verilog’s "c" like syntax provides a structured and logical way to describe digital circuits, making it a go-to choice for hardware designers. Its key syntactic elements are lexical conventions, modules, data types, assignments, procedural blocks, and control structures enable precise and efficient modeling of digital systems.

1. Lexical Conventions: 

• Lexical Conventions consider as "Basics of Verilog Code".
• Verilog syntax is built on tokens (comments, keywords, numbers, strings, identifiers, whitespace), with every statement ending in a semicolon (;).

Case Sensitivity

Verilog is case-sensitive, so rd_clk and rd_CLK are distinct identifiers.

reg rd_clk;  // Different from rd_CLK
reg rd_CLK;   

Comments

Single line: Starts with // ignoring the rest of the line.

Multi-line: Starts with /* and ends with */. Cannot be nested, but single-line comments are allowed inside.

// Single-line comment
integer vlsi; // Declares variable vlsi

/* Multi-line
   comment */

Whitespace

Spaces, tabs, newlines, and form feeds are ignored except to separate tokens or within strings, aiding readability.

module         dut; // Whitespace ignored
  reg [8*6:1] addr = "AB C D"; // Spaces in string preserved
endmodule

Operators

• Unary: Precede the operand (ex, x = ~y; for bitwise NOT).
• Binary: Appear between operands (ex, x = y & z; for bitwise AND).
• Ternary (Conditional): Uses ?: (ex, x = (y > 5) ? w : z;).

Numbers

Numbers can be decimal (default), binary, octal, or hexadecimal. Sized numbers use [size]'[base][number].

16;         // Decimal 16
4'b1010;    // Binary, value = 10
8'hA;       // Hex, value = 10
-6'd3;      // Negative, two’s complement
32'hFACE_47B2; // Underscore for readability

Strings

Strings, enclosed in quotes (" "), store 1 byte per character and cannot span multiple lines.

reg [8*12:1] msg = "Hello World!"; // 12 bytes

Identifiers

Identifiers use alphanumeric characters, _, or $, but cannot start with a digit or $.

reg var_a;    // Valid
reg v$ar_a;   // Valid
reg $var;     // Invalid

Keywords

Reserved lowercase words (ex, module, reg, always) define Verilog constructs and cannot be identifiers.

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2. Modules: Structuring Hardware Designs

A module encapsulates a hardware component, defining its inputs, outputs, and logic.

module module_name (
    input wire a,
    input wire b,
    output reg c
);
    // Logic here
endmodule

Example: A 2-input AND gate:

module and_gate (
    input wire a,
    input wire b,
    output wire y
);
    assign y = a & b;
endmodule

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3. Data Types

Verilog data types model hardware behavior:

• wire: For combinational connections.
  • Example: wire [7:0] bus;
• reg: For storage in procedural blocks (not always a register).
  • Example: reg [3:0] counter;
• integer: 32-bit signed value for simulation.
  • Example: integer i;
• Vectors: Multi-bit signals (ex, [7:0]).

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4. Assignments

Assignments drive signal values:

Continuous Assignment

For combinational logic, using assign outside procedural blocks.

assign y = a ^ b; // XOR

Procedural Assignment

For reg variables in always or initial blocks.

• Blocking (=): Sequential execution.
• Non-blocking (<=): Updates after the block, suited for sequential logic.

  always @(posedge clk) begin
      counter <= counter + 1; // Non-blocking
  end

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Best Practices for Verilog Syntax

• Clear Naming: Use clk, data_out for readability.
• Consistent Formatting: Indent and align code.
• Comment Thoroughly: Use // or /* */ to explain logic.
• Explicit Numbers: Specify sizes (ex, 8'hFF).
• Separate Logic Types: Use always @(*) for combinational, always @(posedge clk) for sequential.
• Test Extensively: Simulate with testbenches to verify behavior.